Comp.Lang.Vhdl

Subjects, that are frequently discussed here:

• Version Control Software (16)
• Best Async FIFO Implementation (15)
• Converting C to VHDL (11)
• Testbench using Modelsim/VHDL - simple signal generation problem (11)
• How to handle floating inputs in a device? (10)
• Auto allocation of Indexes (9)
• PCI-X Core (9)
• How to run Modelsim for VHDL without using GUI.. (8)
• active-hdl state machine editor (7)
• Bus direction (7)

Related Groups: Messages, that appear in this Group also appear in

• comp.arch.fpga (624)
• comp.lang.verilog (379)
• sci.electronics.design (130)
• comp.cad.synthesis (91)

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