Comp.Lang.Verilog

Subjects, that are frequently discussed here:

• Synthesizable FSM (30)
• Modelsim XE, what's the latest version? (15)
• State machine style. (15)
• signed arithmetic (10)
• =?iso-8859-1?q?Re:_IEEE_Standard_Verilog=AE_Hardware_Description_Language?= (8)
• Synthesis warning... (8)
• best way to simulate multi core architecture ? (7)
• blocking with intra delay (7)
• Part Selects in verilog (7)
• about relational greater operator (6)

Related Groups: Messages, that appear in this Group also appear in

• comp.lang.vhdl (471)
• comp.arch.fpga (415)
• comp.cad.cadence (118)
• sci.electronics.design (106)

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